1. Technical Field
The embodiments described herein relate to a semiconductor memory apparatus, and more particularly, to a local skew detecting circuit for implementation in a semiconductor memory apparatus.
2. Related Art
As a design rule in the fabrication of semiconductor memory apparatus, it is important to monitor certain characteristic changes that can occur as the size of the wafer and the wafer process are reduced. In particular, a critical dimension (CD) of a transistor is an important factor that must be accounted for in the layout of a semiconductor apparatus. The critical dimension (CD) is a minimum dimension required in a width of a pattern that is formed on the wafer.
Two types of skew can effect the fabrication of a semiconductor memory apparatus: local skew, which is generated in relation to a single chip; and global skew which will have a different characteristic for each wafer.
Global skew typically refers to distortions or changes in the physical characteristics of transistors that result from changes in PVT (Process, Voltage, and Temperature) during the fabrication of the wafer. The global skew can create different signal skews for each chip on the wafer. The local skew means that the signal skew is different among circuits of the same function according to the locations (i.e. center, right, and left) in a chip. That is, the critical dimension (CD) of the gate width and the threshold voltage (Vt) are changed according to a location in a chip in the semiconductor memory apparatus, which changes the operating parameters for, e.g., a MOS transistor according to the location.
Accordingly, even circuits that perform the same function, and have the same operating characteristics may behave differently according to the locations thereof.